library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity CSA is
generic (N : integer);
port (	A	: in   std_logic_vector(N-1 downto 0);
		B	: in   std_logic_vector(N-1 downto 0);
		Cin	: in   std_logic;
		S	: out std_logic_vector(N-1 downto 0);
		Cout: out std_logic
);
end CSA;

architecture Structural of CSA is

component MUX21 is
port (	A	: in   std_logic;
		B	: in   std_logic;
		S	: in   std_logic;
		O	: out std_logic
);
end component;

component muxer is
generic (N : integer := 32);
port (	data_0	: in   std_logic_vector (N-1 downto 0);
		data_1	: in   std_logic_vector (N-1 downto 0);
		sel 		: in   std_logic;
		output	: out std_logic_vector (N-1 downto 0)
);
end component;

component RCA is
generic (N : integer := 8);
port (	A_rca	: in   std_logic_vector (N-1 downto 0);
		B_rca	: in   std_logic_vector (N-1 downto 0);
		S_rca	: out std_logic_vector (N-1 downto 0);
		C_i		: in   std_logic;
		C_o		: out std_logic
);
end component;

signal Ci		: std_logic_vector (N/4 downto 0);
signal Co_c0	: std_logic_vector (N/4-1 downto 0);
signal Co_c1	: std_logic_vector (N/4-1 downto 0);
signal S_c0	: std_logic_vector (N-1 downto 0);
signal S_c1	: std_logic_vector (N-1 downto 0);
  
begin

	Ci(0)	<= Cin;
	Cout	<= Ci(N/4);

	BLOCK_i: for i in 0 to N/4-1 generate

		RCA4_c0_i : RCA generic map (4) port
		map (	A_rca	=> A(((i+1)*4-1) downto i*4),
				B_rca	=> B(((i+1)*4-1) downto i*4),
				C_i		=> '0',
				S_rca	=> S_c0(((i+1)*4-1) downto i*4),
				C_o		=> Co_c0(i)
			);
		RCA4_c1_i : RCA generic map (4) port
		map (	A_rca	=> A(((i+1)*4-1) downto i*4),
				B_rca	=> B(((i+1)*4-1) downto i*4),
				C_i		=> '1',
				S_rca	=> S_c1(((i+1)*4-1) downto i*4),
				C_o		=> Co_c1(i)
			);

		MUX_S_i : muxer generic map (4) port
		map (	data_0	=> S_c0(((i+1)*4-1) downto i*4),
				data_1	=> S_c1(((i+1)*4-1) downto i*4),
				sel		=> Ci(i),
				output	=> S(((i+1)*4-1) downto i*4)
			);
		MUX_c_i: MUX21 port
		map (	A	=> Co_c1(i),
				B	=> Co_c0(i),
				S	=> Ci(i),
				O	=> Ci(i+1)
			);

			end generate;  

end Structural;
